1. Field of the Invention
This invention relates to phase-locked loops, and more particularly to phase-locked loops with selectable input clock signals.
2. Description of the Related Art
In optical communication systems, line cards compliant with standards such as Synchronous Optical Network (SONET) or Synchronous Digital Hierarchy (SDH) (the European counterpart to SONET), utilize clock generation circuits to generate clocks used in data transmission and reception. In such clock generation circuits, a phase-locked loop (PLL) receives an input reference clock and generates one or more high speed clocks suitable for use in transmitting or receiving data in a SONET(or SDH) based system. According to one aspect of such a communication system, multiple reference clocks may be supplied to a clock generation circuit to provide a variety of capabilities, including redundancy. When the PLL in the clock generation circuit switches from using one input reference clock to using another input reference clock, it is important that there not be a significant change in the phase of the PLL output clock. Phase changes in the output clock due to switching input clocks can lead to problems such as transmission errors. Such a phase glitch may arise when switching clocks, due to the fact that the phase relationship between the two input clocks can be arbitrary. In one system, the amount of allowed phase glitch is specified in FIGS. 5-19 in GR 253-CORE.
In order to avoid a phase glitch when switching between input clocks, one approach to achieve such xe2x80x9chitless switchingxe2x80x9d is to set the bandwidth of the PLL used to multiply the reference clock to be very low, e.g., on the order of Hz. With the low bandwidth PLL, even if the phase difference between the input clocks is relatively large, the phase change resulting from switching input reference clocks used by the PLL would occur relatively slowly. Such a low bandwidth PLL implementation can meet the tight phase transient requirements and thereby minimize transmission errors associated switching reference clocks. However, low bandwidth PLLs suitable for meeting tight phase transient requirements may be difficult to implement in a monolithic integrated circuit, and expensive or difficult to implement with discrete components.
Accordingly, it would be desirable to provide a technique that is more readily implemented in monolithic integrated circuits that avoids phase glitches when switching between input reference clocks and thus meets tight phase transient requirements.
Accordingly, in one embodiment, the phase difference between a feedback signal derived from the output of the PLL and a non-selected input clock is monitored and stored. When a switch occurs to using the non-selected input clock, the stored phase difference is injected into the phase-locked loop to compensate for the phase difference between the clocks. That phase difference is stored as a DC offset value and may be injected in various places and manners in the phase-locked loop.
In one embodiment, the invention provided a method of switching between a first and second clock signal being utilized as an input clock signal to a phase-locked loop (PLL), the method includes, while the PLL is generating an output signal using the first clock signal as the input clock signal, determining a phase difference between a feedback signal, derived from the output signal, and the second clock signal. The method further includes storing a value indicative of the phase difference and injecting a representation of the stored value into the phase-locked loop in response to switching the input clock signal from the first to the second clock signal. The method may further include injecting the representation of the stored value by summing the representation of the stored value with a current value of the phase difference. Injecting the representation of the stored value may include injecting a DC offset signal into the phase locked loop.
The method as recited may further include reducing the phase difference between the second clock signal and the feedback signal by a fixed amount when a magnitude of the phase difference is above a predetermined threshold. That may be accomplished by dividing the feedback signal by a different value when the magnitude of the phase difference is above the predetermined threshold than when the magnitude of the phase difference is below the predetermined threshold.
In another embodiment an apparatus is provided that includes a phase-locked loop that is coupled to use a selectable one of at least a first and second clock signal as an input clock signal. The apparatus includes a first phase detector circuit coupled to detect a first phase difference between a first feedback signal determined according to an output of the phase-locked loop and the first clock signal and to generate a first phase difference signal indicative thereof. The apparatus further includes a second phase detector circuit coupled to detect a second phase difference between a second feedback signal determined according to the output of the phase-locked loop and the second clock signal and to generate a second phase difference signal indicative thereof. A first storage circuit is coupled to periodically store a representation the first phase difference when the second clock signal is selected as the input clock signal. A first phase difference injecting circuit is coupled to the first storage circuit to inject a representation of the stored phase difference into the phase-locked loop when the first clock signal is selected as the input clock.
The apparatus may further include a first phase compare circuit coupled to compare the first clock signal and the first feedback signal to determine when the first clock signal and the first feedback signal are out of phase by more than a predetermined phase amount and output a phase compare signal indicative thereof. A first variable divider circuit is coupled in a path of the first feedback signal between the output of the phase-locked loop and the first phase detector circuit, a divide ratio of the variable divider circuit being controlled according to the phase compare signal.